In data communication systems, data at the transmitter is usually serialized before delivery to the transmission media of the serial link. Phase Locked Loops (PLL) are most frequently employed to produce the bit clock from the local reference clock running at the parallel data frequency (byte rate) for transmitting data at a higher frequency (bit rate). To serialize N-bit parallel data, a clock running at N times the parallel data (byte) frequency is required. This N-bit parallel data is often the encoded data since channel encoding is necessary prior to transmission to overcome a variety of transmission impairments for correct data recovery to ensure reliable data transfer. The Phase Locked Loop (PLL) used in a transmitting circuit is not as demanding as those used in the receiver circuit for the obvious reason that the input to the PLL is a known frequency from a stable frequency source, however, the problems associated with phase locked loop design such as susceptibility to digital switching noise, and the requirement for analog circuitry and large capacitors and resistors is still present, making it difficult to be integrated with digital functions.
In digital implementations where constant, accurate or calibrated-on-the-fly delays are used to form various time bases, controlled delays are required. In the simultaneously filed related application, "Digital Data Recovery Using Delay Time Rulers," Ser. No. 07/901,335 filed Jun. 19, 1992, the data recovery system does not employ a phase locked loop to first extract a continuously running clock from the data, and then read the data using the recovered clock. It uses what we call discrete "Time Rulers" instead to read the incoming data. The Time Rulers are essentially cascaded digitally adjustable delay units, where each delay unit has the delay equal to half of the bit period T.sub.b of the data frequency. In the prior art, controlled delay is normally obtained by applying an analog signal as the control signal to a circuit, which is often a filtered or smoothed output from a phase detector. Traditional methods of constructing phase detectors and low pass filters are still valid for these type of delay regulations. These circuits are difficult to provide in integrated circuits and susceptible to noise. In our all digital solutions, however, a digital command control code is used to control or "select" the delay value. A finite quantizing error will therefore always exist since the selective delays are discrete values and its accuracy or resolution is determined by the minimum achievable delay values of the basic delay cells.
A need exists for digital methods and apparatus to provide precise delay, which circuits automatically detect delay variations and which generate digital corrective command code for adjusting digital controlled delays on-the-fly while the circuit is in operation, to provide calibrated or regulated time delay elements as the "time ruler" for data transmission, data recovery and various other operations.